Auto-Calibrating TDC for an SoC-FPGA Data Acquisition System

In this paper, an FPGA-based plain delay line time-to-digital converters (TDC) is presented, together with a theoretical model on its timing properties. The TDC features an automated calibration system implemented in the on-chip processor of an SoC-FPGA, uses a low amount of FPGA resources and is therefore suitable for applications requiring a high number of channels, such as time-of-flight positron emission tomography (PET). We first...