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P. Carra
Istituto Nazionale di Fisica Nucleare
ArchitectureData acquisitionCalibrationComputer scienceField-programmable gate array
2Publications
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#1P. Carra (INFN: Istituto Nazionale di Fisica Nucleare)H-Index: 1
#2M. Bertazzoni (INFN: Istituto Nazionale di Fisica Nucleare)H-Index: 1
Last. N. Belcari (INFN: Istituto Nazionale di Fisica Nucleare)H-Index: 7
view all 13 authors...
In this paper, an FPGA-based plain delay line time-to-digital converters (TDC) is presented, together with a theoretical model on its timing properties. The TDC features an automated calibration system implemented in the on-chip processor of an SoC-FPGA, uses a low amount of FPGA resources and is therefore suitable for applications requiring a high number of channels, such as time-of-flight positron emission tomography (PET). We first investigated the importance of calibration and validated the ...
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#1P. Carra (INFN: Istituto Nazionale di Fisica Nucleare)H-Index: 1
#2M. Bertazzoni (INFN: Istituto Nazionale di Fisica Nucleare)H-Index: 1
Last. N. Belcari (INFN: Istituto Nazionale di Fisica Nucleare)H-Index: 7
view all 8 authors...
In this paper a FPGA-based delay line TDC architecture is presented, featuring an automated calibration system. We were able to predict and test experimentally the TDC timing properties. They were shown to be related to the fundamental parameters of the used FPGA technology. In particular, the best achievable time resolution of this specific architecture (plain tapped delay line on FPGA) is set by to about 24 ps by the sum of the setup and hold times of the registers in the FPGA.
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