Original paper
Background calibration techniques for multistage pipelined ADCs with digital redundancy
Volume: 50, Issue: 9, Pages: 531 - 538
Published: Sep 1, 2003
Abstract
The proposed digital background calibration scheme, applicable to multistage (pipelined or algorithmic/cyclic) analog-to-digital converters (ADCs), corrects the linearity errors resulting from capacitor mismatches and finite opamp gain. A high-accuracy calibration is achieved by recalculating the digital output based on each stage's equivalent radix. The equivalent radices are extracted in the background by using a digital correlation method....
Figures & Tables
Fig. 1. 1.5-bit-per-stage pipeline ADC.
Fig. 10. Overall ADC with proposed background digital calibration.
Fig. 11. Prototype two-stage cyclic ADC applying proposed calibration.
Fig. 12. Output spectrum of the prototype ADC before and after calibration.
Fig. 3. Functional diagram of a pipeline ADC (1.5-bit-per-stage).
Fig. 4. “Noncapacitor-flip-over” MDAC.
Fig. 7. Background equivalent radix-extraction scheme 2.
Fig. 8. Interference in the radix-error detection.
Paper Details
Title
Background calibration techniques for multistage pipelined ADCs with digital redundancy
Published Date
Sep 1, 2003
Volume
50
Issue
9
Pages
531 - 538
TrendsPro
You’ll need to upgrade your plan to Pro
Looking to understand a paper’s academic impact over time?
- Scinapse’s Citation Trends graph enables the impact assessment of papers in adjacent fields.
- Assess paper quality within the same journal or volume, irrespective of the year or field, and track the changes in the attention a paper received over time.
Citation AnalysisPro
You’ll need to upgrade your plan to Pro
Looking to understand the true influence of a researcher’s work across journals & affiliations?
- Scinapse’s Top 10 Citation Journals & Affiliations graph reveals the quality and authenticity of citations received by a paper.
- Discover whether citations have been inflated due to self-citations, or if citations include institutional bias.