Digital Background Calibration for Pipelined ADCs Based on Comparator Decision Time Quantization

This brief presents a digital background calibration technique that embraces comparator decision time to calibrate interstage gain errors and capacitor mismatches in pipelined analog-to-digital converters (ADCs). It does not modify the original analog signal path except for the addition of a comparator decision time binary quantizer built by simple digital gates. The technique does not limit either the ADC input signal swing or bandwidth....