Original paper
500-MS/s 5-bit ADC in 65-nm CMOS With Split Capacitor Array DAC
Volume: 42, Issue: 4, Pages: 739 - 747
Published: Apr 1, 2007
Abstract
A 500-MS/s 5-bit ADC for UWB applications has been fabricated in a 65-nm CMOS technology using no analog-specific processing options. The time-interleaved successive approximation register (SAR) architecture has been chosen due to its simplicity versus flash and its amenability to scaled technologies versus pipelined, which relies on operational amplifiers. Six time-interleaved channels are used, sharing a single clock operating at the composite...
Paper Details
Title
500-MS/s 5-bit ADC in 65-nm CMOS With Split Capacitor Array DAC
Published Date
Apr 1, 2007
Volume
42
Issue
4
Pages
739 - 747
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