Original paper
A digitally enhanced 1.8-V 15-bit 40-MSample/s CMOS pipelined ADC
Volume: 39, Issue: 12, Pages: 2126 - 2138
Published: Nov 30, 2004
Abstract
A 1.8-V 15-bit 40-MSample/s CMOS pipelined analog-to-digital converter with 90-dB spurious-free dynamic range (SFDR) and 72-dB peak signal-to-noise ratio (SNR) over the full Nyquist band is presented. Its differential and integral nonlinearities are 0.25 LSB and 1.5 LSB, respectively, and its power consumption is 400 mW. This performance is enabled by digital background calibration of internal digital-to-analog converter (DAC) noise and...
Paper Details
Title
A digitally enhanced 1.8-V 15-bit 40-MSample/s CMOS pipelined ADC
Published Date
Nov 30, 2004
Volume
39
Issue
12
Pages
2126 - 2138
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