Parasitic Suppression in 2D Smart Power ICs Using Deep Trench Isolation: A Simulation Study

In this letter, a planar integration using the deep trench isolation (DTI) technique is proposed to suppress the inter-well parasites in smart power integrated circuits implemented in 0.35 µm BiCMOS technology. In this technology, all devices share the same epitaxial layer. This can lead to a punch-through between power devices as well as between power and low-voltage CMOS devices. A DTI scheme is used to suppress the effect of the parasitic BJT...