Vertical Tunnel Field-Effect Transistor with Polysilicon Layer

Volume: 19, Issue: 10, Pages: 6722 - 6726
Published: Oct 1, 2019
Abstract
In this paper, a novel structure of tunnel field-effect transistors (TFETs) is proposed. The proposed device has an intrinsic polysilicon layer located in the overlap region between the source and the gate, which can increase the tunneling area and overcome the low ON-current drawback of the conventional TFET. The advantages of the proposed device are proven by using technology computeraided design (TCAD) simulation. It exhibits more than 50...
Paper Details
Title
Vertical Tunnel Field-Effect Transistor with Polysilicon Layer
Published Date
Oct 1, 2019
Volume
19
Issue
10
Pages
6722 - 6726
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