Original paper
Low-power dual-modulus frequency divider by 4/5 up to 13-GHz in 0.13μm CMOS
Pages: 1 - 4
Published: Nov 1, 2017
Abstract
This paper presents a dual-modulus flip-flop-based frequency divider with programmable division ratios by 4/5 designed in a 0.13 μm CMOS technology. The divider is based on a modified CML D-latch topology, for high speed operation and a low power consumption. The AND gates used for realization of dual-modulus operation are integrated directly into the D-latches to achieve low power consumption and minimum gate delay. This modified circuit...
Paper Details
Title
Low-power dual-modulus frequency divider by 4/5 up to 13-GHz in 0.13μm CMOS
Published Date
Nov 1, 2017
Pages
1 - 4
References
Notes
History