Low‐power successive approximation ADC using split‐monotonic capacitive DAC

This paper presents a low-power 10-bit 50-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) that uses a monotonic capacitor switching procedure. Compared to converters that use the conventional procedure, the average switching energy and total capacitance are reduced by about 81% and 50%, respectively. In the switching procedure, the input common-mode voltage gradually converges to ground. An improved comparator diminishes the signal-dependent offset caused by the in...

A 1.2 V 10-bit 100 MS/s Successive Approximation (SA) ADC is presented. The scheme achieves high-speed and low-power operation thanks to the reference-free technique that avoids the static power dissipation of an on-chip reference generator. Moreover, the use of a common-mode based charge recovery switching method reduces the switching energy and improves the conversion linearity. A variable self-timed loop optimizes the reset time of the preamplifier to improve the conversion speed. Measurement...

A 500-MS/s 5-bit ADC for UWB applications has been fabricated in a 65-nm CMOS technology using no analog-specific processing options. The time-interleaved successive approximation register (SAR) architecture has been chosen due to its simplicity versus flash and its amenability to scaled technologies versus pipelined, which relies on operational amplifiers. Six time-interleaved channels are used, sharing a single clock operating at the composite sampling rate. Each channel has a split capacitor ...

This paper describes an ultra-low power SAR ADC for medical implant devices. To achieve the nano-watt range power consumption, an ultra-low power design strategy has been utilized, imposing maximum simplicity on the ADC architecture, low transistor count and matched capacitive DAC with a switching scheme which results in full-range sampling without switch bootstrapping and extra reset voltage. Furthermore, a dual-supply voltage scheme allows the SAR logic to operate at 0.4 V, reducing the overal...

A novel low-energy tri-level switching scheme for low-power successive approximation register (SAR) ADC is proposed. With the input common-mode voltage (Vcm) designed to be exactly half of the reference voltage (Vref), the switching energy of the proposed switching scheme is reduced by 96.89% as compared with the conventional architecture. Besides the large energy saving, the proposed switching scheme also reduces the number of capacitors in the ADC capacitor array by 75%, which in turn results ...

A novel energy-efficient VCM-based monotonic capacitor switching scheme for successive approximation register (SAR) analogue to-digital converters (ADCs) is proposed. Based on the third reference voltage VCM and monotonic capacitor switching procedure, the proposed switching scheme achieves 97.66% less switching energy and 75% less number of capacitors over the conventional architecture, resulting in the most energy-efficient switching scheme among the reported switching sequences.

This paper presents a 10-bit ultra-low power successive approximation register (SAR) analog-to-digital converter (ADC) for implantable medical devices. To achieve the nanowatt range power consumption, a novel switching scheme is proposed, which can accomplish the first three comparisons without consuming any energy and thus improve the energy efficiency significantly. In addition, to boost the offset performance of the comparator working under low supply voltage, a detailed theoretical analysis ...

A high energy-efficiency switching scheme for a successive approximation register (SAR) analogue-to-digital converter (ADC) is presented. The proposed method can achieve 98.4% savings in switching energy when compared to a conventional SAR. The proposed technique also achieves a 4 × reduction in total capacitance used in the digital-to-analogue converter (DAC) compared to the conventional DAC.

A 12-bit 10 MS/s SAR ADC with enhanced linearity and energy efficiency is presented in this paper. A novel switching scheme (COSS) is proposed to reduce the power consumption and the matching requirement for capacitors in SAR ADCs. The switching energy (including switching energy and reset energy), total capacitance and static performance (INL & DNL) of the proposed scheme are reduced by 98.08%, 75%, and 75%, respectively, compared with the conventional architecture. Based on analysis of the non...

A novel low-energy hybrid capacitor switching scheme for a low-power successive approximation register (SAR) analogue-to-digital converter (ADC) is presented. The proposed switching scheme combines a new switch method and the monotonic technique. The new switch method can achieve no switching energy consumption in the first three comparison cycles. Furthermore, a low-energy monotonic procedure is performed for the rest of the comparisons. The average switching energy is reduced by 98.83% compare...