Vref optimization in DDR4 RDIMMs for improved timing margins

JEDEC DDR4 SDRAM adopted the internal Data (DQ) reference voltage (VREFDQ) generation scheme as opposed to DDR3 SDRAM where VREF was generated by an external device that produced fixed (constant) voltage irrespective of the loading on the device, power supply variations, temperature changes, and the passage of time. With the introduction of Per DRAM Addressability (PDA) in DDR4 memory and the internal VREF combined, discussed in this paper is a...