Predict VLSI Circuit Reliability Risks Using Neural Network
Published on Jan 1, 2014
· DOI :10.13189/ujes.2014.020502
This paper describes the challenges faced in predicting the reliability of very large scale integration (VLSI) circuits. Currently, lots of trial-and-errors are still needed for the parameters selected to develop a neural network prediction model, whose result is with a great deal of uncertainty. The objective of this paper is to provide a novel and practical approach to design a reliability prediction model using neural network. We propose a seven-step procedure to formulate an optimal neural network design and explain it in details using a case study on semiconductor reliability. We combine reliability test characteristics (e.g., early failures) with statistical methods such as regression and design of experiment (DOE) for this optimal neural network model and get comparably small prediction errors. Following our proposed approach, analysts can develop effective designs with higher prediction accuracy. We further introduce an operation flow to maximize the benefits from the obtained optimal prediction model by earlier nonconformance detection and faster lot dispositions, which are reported in the case study on successfully implementing our methodology to predict inter metal dielectric (IMD) reliability risks. Our proposed approach can be easily applied on many other fields like yield prediction.