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Predict VLSI Circuit Reliability Risks Using Neural Network

Published on Jan 1, 2014
· DOI :10.13189/ujes.2014.020502
Wei-Ting Kary Chien1
Estimated H-index: 1
,
Randy Kang1
Estimated H-index: 1
+ 1 AuthorsMing Li23
Estimated H-index: 23
Cite
Abstract
This paper describes the challenges faced in predicting the reliability of very large scale integration (VLSI) circuits. Currently, lots of trial-and-errors are still needed for the parameters selected to develop a neural network prediction model, whose result is with a great deal of uncertainty. The objective of this paper is to provide a novel and practical approach to design a reliability prediction model using neural network. We propose a seven-step procedure to formulate an optimal neural network design and explain it in details using a case study on semiconductor reliability. We combine reliability test characteristics (e.g., early failures) with statistical methods such as regression and design of experiment (DOE) for this optimal neural network model and get comparably small prediction errors. Following our proposed approach, analysts can develop effective designs with higher prediction accuracy. We further introduce an operation flow to maximize the benefits from the obtained optimal prediction model by earlier nonconformance detection and faster lot dispositions, which are reported in the case study on successfully implementing our methodology to predict inter metal dielectric (IMD) reliability risks. Our proposed approach can be easily applied on many other fields like yield prediction.
  • References (10)
  • Citations (3)
Cite
References10
Newest
Wei-Ting Kary Chien1
Estimated H-index: 1
,
Zhao Yong Atman1
Estimated H-index: 1
+ 1 AuthorsJeff Wu3
Estimated H-index: 3
Traditionally, to assess reliability lifetimes and to evaluate reliability performance of semiconductor devices and chips, we test the samples to their failures. This can be called the "Test-to-Fail" scenario, which usually takes a long time (e.g., longer than a week). The Test-to-Failure scenario is required especially at the qualification stage, whose objective is to obtain the lifetimes of, e.g., devices, dielectrics, and metal lines. Due to the long test times, this approach is inadequate fo...
Published on Aug 1, 2012
Shuzhi Li1
Estimated H-index: 1
(Xi'an Jiaotong University),
Guanghua Xu15
Estimated H-index: 15
(Xi'an Jiaotong University),
Yongbao Feng1
Estimated H-index: 1
In order to solve the problem of low efficiency and low reliability of Gaussian Bayesian network structure learning methods, this paper proposes a new Gaussian Bayesian network structure learning algorithm from data based on the canonical correlation analysis. Firstly, by canonical correlation analysis of the son node and the candidate parent nodes, the correlation coefficients and correlation variables are given. Because the correlation coefficient indicates the association strength of family s...
Published on Aug 1, 2004in Microelectronics Reliability 1.48
Summer Tseng2
Estimated H-index: 2
(SJTU: Shanghai Jiao Tong University),
Wei-Ting Kary Chien3
Estimated H-index: 3
(Semiconductor Manufacturing International Corporation)
+ 2 AuthorsBing-Chu Cai2
Estimated H-index: 2
(SJTU: Shanghai Jiao Tong University)
In this paper, some practical considerations for effective and efficient wafer-level reliability control (WLRC) are presented. We propose a better solution to replace the previous method by adding a protection diode to avoid process induced charging damage on test structure devices. This work also provides in-depth discussions on WLR Via electromigration (EM), which correlated well with traditional time-consuming package-level tests. In addition, due to the time constraint at WLRC, some real cas...
Published on May 1, 2003in Microelectronics Reliability 1.48
Summer Tseng2
Estimated H-index: 2
(SJTU: Shanghai Jiao Tong University),
Wei-Ting Kary Chien3
Estimated H-index: 3
,
Bing-Chu Cai2
Estimated H-index: 2
(SJTU: Shanghai Jiao Tong University)
Abstract This paper depicts the improvement of poly-silicon (poly-Si) holes induced failures during gate oxide integrity (GOI) voltage-ramp (V-Ramp) tests by replacing plasma enhanced oxidation with silicon rich oxidation (SRO), which is cap oxide on transfer gate serving as a hard mask to selectively form salicide. The SRO was found to be capable of completely removing salicide block etching induced poly-Si holes. With this SRO film deposited on poly-gate, the higher density silicon in cap oxid...
Published on Dec 1, 2002in IEEE Transactions on Reliability 2.89
Wei-ting Kary Chen1
Estimated H-index: 1
,
Charles Hung-Jia Huang1
Estimated H-index: 1
To cope with the fast advancement of the semiconductor technology and customers' expectations toward performance, service, delivery, quality and reliability, it is necessary to identify defect lots earlier in the production lines. This makes the conventional package-level reliability tests unsuitable for the modern semiconductor industries due to the long cycle time. The BIR (building-in reliability) methodology, on the contrary, preserves the merits of fast response, early alarm and closed-loop...
Published on Jan 1, 2000
Howard B. Demuth11
Estimated H-index: 11
,
Mark Beale7
Estimated H-index: 7
Published on Oct 15, 1998
Steve Lawrence45
Estimated H-index: 45
,
C. Lee Giles65
Estimated H-index: 65
,
Ah Chung Tsoi29
Estimated H-index: 29
Published on Jan 1, 1998in Soil Science Society of America Journal 2.00
Marcel G. Schaap33
Estimated H-index: 33
(USDA: United States Department of Agriculture),
Feike J. Leij29
Estimated H-index: 29
(USDA: United States Department of Agriculture),
Martinus Th. van Genuchten31
Estimated H-index: 31
(USDA: United States Department of Agriculture)
The solution of many field-scale flow and transport problems requires estimates of unsaturated soil hydraulic properties. The objective of this study was to calibrate neural network models for prediction of water retention parameters and saturated hydraulic conductivity, K s , from basic soil properties. Twelve neural network models were developed to predict water retention parameters using a data set of 1209 samples containing sand, silt, and clay contents, bulk density, porosity, gravel conten...
Published on Jan 1, 1998in Technometrics 2.09
Way Kuo18
Estimated H-index: 18
(UC Davis: University of California, Davis),
Taeho Kim5
Estimated H-index: 5
,
Wei-Ting Kary Chien4
Estimated H-index: 4
From the Publisher: Reliability, Yield, and Stress Burn-In explains reliability issues in Microelectronics Systems Manufacturing and Software Development with an emphasis on evolving manufacturing technology for the semiconductor industry. Since most microelectronics components have their infant mortality period for about one year under the ordinary operating conditions, and many of the modern systems, such as the PC's, are heavily used in the first few years, the reliability problem at the infa...
Igor V. Tetko42
Estimated H-index: 42
,
David J. Livingstone28
Estimated H-index: 28
,
A. I. Luik6
Estimated H-index: 6
The application of feed forward back propagation artificial neural networks with one hidden layer (ANN) to perform the equivalent of multiple linear regression (MLR) has been examined using artificial structured data sets and real literature data. The predictive ability of the networks has been estimated using a training/ test set protocol. The results have shown advantages of ANN over MLR analysis. The ANNs do not require high order terms or indicator variables to establish complex structure-ac...
Cited By3
Newest
Published on Dec 1, 2016
Sheng Kang1
Estimated H-index: 1
,
Wei-Ting Kary Chien1
Estimated H-index: 1
,
Jun Gang Yang1
Estimated H-index: 1
(SJTU: Shanghai Jiao Tong University)
The semiconductor industry as one of the world's most automated and advanced manufacturing produces a huge variety of data every day. How to maximize the usage of these data is what we want to discuss in this paper. A big-data platform and its applications for semiconductor manufacturing based on Hadoop framework are proposed. Hadoop is a distributed data storage and computing solution with related low hardware cost and high system reliability. It is a great significance to conducting Hadoop pla...
Published on Jan 1, 2016in Materials Science in Semiconductor Processing 2.72
Chinte Kuo (Fudan University), David Wei Zhang22
Estimated H-index: 22
(Fudan University)
+ 2 AuthorsAlbert Pang
Abstract Tiny defects may escape from in-line defect scan and pass WAT (Wafer Acceptance Test), CP (Chip Probing), FT (Final Test) and SLT (System Level Test). Chips with such kind of defects will cause reliability problem and impact revenue significantly. It is important to catch the defects and derive the prevention strategy earlier in the technology development stage. In this paper, we investigate an SRAM with tiny defects which passed in-line defect scan, WAT, CP and FT but failed in HTOL (H...
Wei-Ting Kary Chien1
Estimated H-index: 1
,
Yong Atman Zhao1
Estimated H-index: 1
+ 1 AuthorsMing Li2
Estimated H-index: 2
Reliability assessment is very important in semiconductor manufacturing, and we need to setup and maintain an efficient and effective reliability baseline (BL) management system to, for example, assess reliability risks, to dispose impacted lots, and to release equipment. To achieve these goals, we propose a corresponding flow and pinpoint the critical points to establish and maintain reliability BLs. To provide insights to readers by actual cases on reliability BL analyses and applications, we ...