Original paper
A 14-bit 20-MS/s Pipelined ADC With Digital Distortion Calibration
Volume: 41, Issue: 11, Pages: 2417 - 2423
Published: Oct 30, 2006
Abstract
A new digital distortion calibration technique is demonstrated in a 14-bit 20-MS/s pipelined analog-to-digital converter (ADC). Calibration parameters are obtained in a way similar to conventional digital gain calibration. The prototype ADC has been fabricated in a 0.18-mum CMOS process and consumes 33.7 mW at 2.8 V. Using the proposed calibration method, a 15-dB improvement of the third-order harmonic rejection is achieved. The measured SNDR...
Paper Details
Title
A 14-bit 20-MS/s Pipelined ADC With Digital Distortion Calibration
Published Date
Oct 30, 2006
Volume
41
Issue
11
Pages
2417 - 2423
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