Original paper
A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure
Volume: 45, Issue: 4, Pages: 731 - 740
Published: Mar 24, 2010
Abstract
This paper presents a low-power 10-bit 50-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) that uses a monotonic capacitor switching procedure. Compared to converters that use the conventional procedure, the average switching energy and total capacitance are reduced by about 81% and 50%, respectively. In the switching procedure, the input common-mode voltage gradually converges to ground. An improved comparator...
Figures & Tables
Fig. 1. A conventional 10-bit SAR ADC.
Fig. 10. DAC control logic.
Fig. 11. (a) Sandwich capacitor. (b) Multi-layer sandwich capacitor.
Fig. 12. The layout floorplan of the capacitor array.
Fig. 13. Die micrograph and the zoomed view.
Fig. 14. Measured DNL and INL.
Fig. 15. Measured 32,768-point FFT spectrum at 50 MS/s.
Fig. 16. Measured dynamic performance versus input frequency at 1.2 V and 50 MS/...
Paper Details
Title
A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure
Published Date
Mar 24, 2010
Volume
45
Issue
4
Pages
731 - 740
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