Wireless networks-on-chips: architecture, wireless channel, and devices

Published on Oct 1, 2012in IEEE Wireless Communications 9.20
· DOI :10.1109/MWC.2012.6339473
David W. Matolak13
Estimated H-index: 13
(Ohio University),
Avinash Karanth Kodi16
Estimated H-index: 16
(Ohio University)
+ 3 AuthorsWilliam Rayess5
Estimated H-index: 5
(Ohio University)
Abstract
Wireless networks-on-chips (WINoCs) hold substantial promise for enhancing multicore integrated circuit performance, by augmenting conventional wired interconnects. As the number of cores per IC grows, intercore communication requirements will also grow, and WINoCs can be used to both save power and reduce latency. In this article, we briefly describe some of the key challenges with WINoC implementation, and also describe our example design, iWISE, which is a scalable wireless interconnect design. We show that the integration of wireless interconnects with wired interconnects in NoCs can reduce overall network power by 34 percent while achieving a speedup of 2.54 on real applications.
  • References (12)
  • Citations (27)
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References12
Published on May 1, 2007in IEEE Journal of Solid-state Circuits 4.08
Denis C. Daly17
Estimated H-index: 17
(Massachusetts Institute of Technology),
Anantha P. Chandrakasan96
Estimated H-index: 96
(Massachusetts Institute of Technology)
A 1-Mb/s 916.5-MHz on-off keying (OOK) transceiver for short-range wireless sensor networks has been designed in a 0.18-mum CMOS process. The receiver has an envelope detection based architecture with a highly scalable RF front-end. Untuned RF circuits are leveraged and optimized in the receiver to achieve superior energy efficiency compared to tuned RF circuits. The receiver power consumption scales from 0.5 mW to 2.6 mW, with an associated sensitivity of -37 dBm to -65 dBm at a BER of 10 -3 . ...
212 Citations Source Cite
Published on May 1, 2010 in Networks-on-Chips
Ruizhe Wu2
Estimated H-index: 2
(University of Louisiana at Lafayette),
Yi Wang3
Estimated H-index: 3
(University of Louisiana at Lafayette),
Dan Zhao1
Estimated H-index: 1
(University of Louisiana at Lafayette)
To bridge the widening gap between computation requirements of terascale application and communication efficiency faced by gigascale multi-processor system-on-chip devices, a new on-chip communication system, dubbed Wireless Network-on-Chip (WNoC), has been proposed. This work centers on the design of a high-efficient, low-cost, deadlock-free routing scheme for domain-specific irregular mesh WNoCs. A distributed minimal table based routing scheme is designed to facilitate segmented XY-routing. D...
14 Citations Source Cite
Published on Jul 1, 2010in IEEE Design & Test of Computers 1.54
Patrick Chiang22
Estimated H-index: 22
(Oregon State University),
Sirikarn Woracheewan3
Estimated H-index: 3
(Oregon State University)
+ 4 AuthorsHuaping Liu22
Estimated H-index: 22
(Oregon State University)
This article advocates the use of short-range wireless communication inside a computing chassis. Ultrawideband links make it possible to design a within-chassis wireless interconnect. In contrast to conventional, fixed, wireline connections between chips, wireless communications offer certain unique advantages, as the authors explain.
27 Citations Source Cite
Published on Oct 1, 2009
Stefaan Decoutere30
Estimated H-index: 30
(Katholieke Universiteit Leuven),
S. Van Huylenbroeck9
Estimated H-index: 9
(Katholieke Universiteit Leuven)
+ 6 AuthorsM. Schroter21
Estimated H-index: 21
The European project DOTFIVE [1] addresses evolutionary scaling of self-aligned selective epitaxial base SiGe:C HBTs, investigates novel SiGe:C HBT architectures, and develops novel process modules to push SiGe BiCMOS towards 500 GHz F max and 2.5 ps gate delay. In this paper, scaling issues of SiGe:C HBT technology will be addressed. The limitations of the different commonly used architectures will be described, and measures taken in the project to overcome these limitations will be summarized....
27 Citations Source Cite
Published on Aug 1, 2011
Xinmin Yu11
Estimated H-index: 11
(Washington State University),
Suman P. Sah7
Estimated H-index: 7
(Washington State University)
+ 3 AuthorsDeukhyoun Heo22
Estimated H-index: 22
(Washington State University)
A highly energy-efficient on-chip communication network is crucial for the development of future multi-core chips. In this paper, a wideband millimeter-wave (mm-wave) transceiver was designed for the wireless Network-on-Chip (WiNoC) architecture. In order to reduce the power consumption of the transceiver, body-enabled circuit design techniques were implemented: Forward body-bias was used in the low-noise amplifier (LNA) and power amplifier (PA) circuits to lower the threshold voltages, reducing...
33 Citations Source Cite
Published on Jan 1, 2010in Infrared Physics & Technology 1.85
Ghanshyam Singh19
Estimated H-index: 19
(Jaypee University of Information Technology)
Abstract The effects of 2-D electromagnetic crystal substrate on the performance of a rectangular microstrip patch antennas at THz frequencies is simulated. Electromagnetic crystal substrate is used to obtain extremely broad-bandwidth with multi-frequency band operation of the proposed microstrip antennas. Multi-frequency band microstrip patch antennas are used in modern communication systems in order to enhance their capacity through frequency reuse. The simulated 10 dB impedance bandwidth of t...
33 Citations Source Cite
Published on Jul 1, 2010 in Application-Specific Systems, Architectures, and Processors
Sujay Deb11
Estimated H-index: 11
(Washington State University),
Amlan Ganguly16
Estimated H-index: 16
(Washington State University)
+ 3 AuthorsDeuk Heo4
Estimated H-index: 4
(Washington State University)
In a traditional Network-on-Chip (NoC), latency and power dissipation increase with system size due to its inherent multi-hop communications. The performance of NoC communication fabrics can be significantly enhanced by introducing long-range, low power, high bandwidth direct links between far apart cores. In this paper a design methodology for a scalable hierarchical NoC with on-chip millimeter (mm)-wave wireless links is proposed. The proposed wireless NoC offers significantly higher throughpu...
68 Citations Source Cite
Published on Oct 1, 2011in IEEE Transactions on Computers 3.05
Amlan Ganguly16
Estimated H-index: 16
(Rochester Institute of Technology),
Kevin Chang10
Estimated H-index: 10
(Washington State University)
+ 3 AuthorsChristof Teuscher18
Estimated H-index: 18
(Portland State University)
Multicore platforms are emerging trends in the design of System-on-Chips (SoCs). Interconnect fabrics for these multicore SoCs play a crucial role in achieving the target performance. The Network-on-Chip (NoC) paradigm has been proposed as a promising solution for designing the interconnect fabric of multicore SoCs. But the performance requirements of NoC infrastructures in future technology nodes cannot be met by relying only on material innovation with traditional scaling. The continuing deman...
196 Citations Source Cite
Steven D. Keller5
Estimated H-index: 5
(Duke University),
W. Devereux Palmer3
Estimated H-index: 3
(Research Triangle Park),
William T. Joines26
Estimated H-index: 26
(Duke University)
An electrically small antenna connected directly to a complementary pair of switching transistors is driven with a pulsewidth modulated HF signal, eliminating the requirement for a frequency-dependent impedance-matching network. The intrinsic reactance of the transmit and receive antennas acts as a filter to recover the HF signal from the digital pulse train. This is defined here as the digitally driven antenna architecture. A circuit simulator with broadband equivalent-circuit models for the tr...
4 Citations Source Cite
Published on Jul 1, 1995 in International Symposium on Computer Architecture
Steven Cameron Woo4
Estimated H-index: 4
(Stanford University),
Moriyoshi Ohara2
Estimated H-index: 2
(Stanford University)
+ 2 AuthorsAnoop Gupta51
Estimated H-index: 51
(Stanford University)
The SPLASH-2 suite of parallel applications has recently been released to facilitate the study of centralized and distributed shared-address-space multiprocessors. In this context, this paper has two goals. One is to quantitatively characterize the SPLASH-2 programs in terms of fundamental properties and architectural interactions that are important to understand them well. The properties we study include the computational load balance, communication to computation ratio and traffic needs, impor...
3,048 Citations Source Cite
Cited By27
Published on Oct 1, 2015in IEEE ACM Transactions on Networking 3.11
Sergi Abadal9
Estimated H-index: 9
(Polytechnic University of Catalonia),
Mario Iannazzo3
Estimated H-index: 3
(Polytechnic University of Catalonia)
+ 3 AuthorsEduardo José Alarcón Cot27
Estimated H-index: 27
(Polytechnic University of Catalonia)
Networks-on-chip (NoCs) are emerging as the way to interconnect the processing cores and the memory within a chip multiprocessor. As recent years have seen a significant increase in the number of cores per chip, it is crucial to guarantee the scalability of NoCs in order to avoid communication to become the next performance bottleneck in multicore processors. Among other alternatives, the concept of wireless network-on-chip (WNoC) has been proposed, wherein on-chip antennas would provide native ...
31 Citations Source Cite
Soumyasanta Laha5
Estimated H-index: 5
(Ohio University),
Savas Kaya16
Estimated H-index: 16
(Ohio University)
+ 3 AuthorsAvinash Karanth Kodi16
Estimated H-index: 16
(Ohio University)
This paper explores the general framework and prospects for on-chip and off-chip wireless interconnects implemented for high-performance computing (HPC) systems in the context of micro power wireless design. HPC interconnects demand very high (≥ 10 Gb/s) transmission rates using ultraefficient ( $\sim ~1$ pJ/bit) transceivers over extremely short (≤ 100 cm) ranges. In an attempt to design such wireless interconnects, first a model for the wireless communication channel properties is developed. T...
15 Citations Source Cite
Published on Jun 1, 2013in IEEE Communications Magazine 9.27
David W. Matolak7
Estimated H-index: 7
(University of South Carolina),
Savas Kaya16
Estimated H-index: 16
(Ohio University),
Avinash Karanth Kodi16
Estimated H-index: 16
(Ohio University)
Designing and implementing wireless networks on chips (WiNoCs) presents numerous engineering challenges, in the areas of computer architecture, multiple access, wireless propagation, physical layer communications processing, and device design and fabrication. In this article we provide a survey on WiNoC propagation and the issues involved with WiNoC channel modeling. We address both attenuation and dispersion, and illustrate the dramatic differences between the miniature WiNoC case and more fami...
17 Citations Source Cite
Published on Dec 13, 2014
Sergi Abadal9
Estimated H-index: 9
,
Albert Mestres6
Estimated H-index: 6
+ 3 AuthorsAlbert Cabellos-Aparicio16
Estimated H-index: 16
Network-on-Chip (NoC) is currently the paradigm of choice for covering the on-chip communication needs of multicore processors. As we reach the manycore era, though, electrical interconnects present performance and power issues that are exacerbated in the presence of multicast communications due to the point-to-point nature of NoCs. This dramatically limits the available design space in terms of manycore architecture, sparking the need for new solutions. In this direction, the use of wireless in...
2 Citations Source Cite
Published on Jan 1, 2014in IEICE Transactions on Electronics 0.52
Shijun Lin3
Estimated H-index: 3
(Xiamen University),
Zhaoshan Liu (Xiamen University)+ 1 AuthorsXiaofang Wu (Xiamen University)
Source Cite
Published on Aug 1, 2015in The Journal of Supercomputing 1.53
Abbas Dehghani2
Estimated H-index: 2
(University of Isfahan),
Kamal Jamshidi9
Estimated H-index: 9
(University of Isfahan)
Wireless network on chip (WNoC) is a promising new solution for overcoming the constraints in the traditional electrical interconnections. However, the occurrence of faults has become more prevalent because of the continuous shrinkage of CMOS technology and integration of wireless technology in such complex circuits. This can lead to formation of faulty regions on chip, where the probability of the entire system failure increases in a significant manner. This issue is not addressed in the previo...
5 Citations Source Cite
Published on Sep 28, 2015 in Networks-on-Chips
Sergi Abadal9
Estimated H-index: 9
,
Mario Nemirovsky12
Estimated H-index: 12
(Barcelona Supercomputing Center)
+ 1 AuthorsAlbert Cabellos-Aparicio16
Estimated H-index: 16
The cost of broadcast has been constraining the design of manycore processors and of the algorithms that run upon them. However, as on-chip RF technologies allow the design of small-footprint and high-bandwidth antennas and transceivers, native low-latency (a few clock cycles) and low-power (a few pJ/bit) broadcast support through wireless communication can be envisaged. In this paper, we analyze the main networking design aspects and challenges of Broadcast-oriented Wireless Network-on-Chip (Bo...
3 Citations Source Cite
Ke Guan17
Estimated H-index: 17
(Beijing Jiaotong University),
Bo Ai22
Estimated H-index: 22
(Beijing Jiaotong University)
+ 4 AuthorsThomas Kurner27
Estimated H-index: 27
(Braunschweig University of Technology)
The ever decreasing geometrical dimensions of electronic devices makes miscellaneous cables or connectors of relatively large dimensions unwanted. Thus, wireless inter/intra-device communications in the millimeter-wave range become a topic of recent interest. In this paper, the excess losses of three groups of typical semi-closed obstacles (connectors, heatsinks, and printed circuit boards) in inter/intra-device communications are measured and empirically modeled. Specific coefficients for each ...
7 Citations Source Cite
Abbas Dehghani2
Estimated H-index: 2
(University of Isfahan),
Kamal Jamshidi9
Estimated H-index: 9
(University of Isfahan)
Wireless Network-on-Chip (WNoC) architectures have emerged as a promising interconnection infrastructure to address the performance limitations of traditional wire-based multihop NOCs. Nevertheless, the WNoC systems encounter high failure rates due to problems pertaining to integration and manufacturing of wireless interconnection in nano-domain technology. As a result, the permanent failures may lead to the formation of any shape of faulty regions in the interconnection network, which can break...
2 Citations Source Cite
Published on Mar 25, 2016 in Architectural Support for Programming Languages and Operating Systems
Sergi Abadal9
Estimated H-index: 9
(University of Illinois at Urbana–Champaign),
Albert Cabellos-Aparicio16
Estimated H-index: 16
(Polytechnic University of Catalonia)
+ 1 AuthorsJosep Torrellas51
Estimated H-index: 51
(University of Illinois at Urbana–Champaign)
In shared-memory multiprocessing, fine-grain synchronization is challenging because it requires frequent communication. As technology scaling delivers larger manycore chips, such pattern is expected to remain costly to support. In this paper, we propose to address this challenge by using on-chip wireless communication. Each core has a transceiver and an antenna to communicate with all the other cores. This environment supports very low latency global communication. Our architecture, called WiSyn...
10 Citations Source Cite