IEEE Transactions on Electron Devices
Papers 23029
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The realization of high- {k}/IL/Ge MOS interfaces with thin equivalent oxide thickness (EOT), low interface state density ( \text{D}_{{\text {it}}}), and high reliability is strongly needed for realizing Ge metal–oxide–semiconductor field-effect transistors (MOSFETs). In this article, we examine the properties of the slow trap areal density ( \Delta \text{N}_{{\text {st}}}) and \text{D}_{{\text {it}}}in Al2O3/GeOxN y /n-Ge MOS interfaces formed by atomic layer deposition (ALD) Al2O3 ...
A 2-D electrothermal model of delta-doped b eta-gallium oxide ( \beta -Ga2O3) metal–semiconductor field-effect transistor (MESFET) is developed by using TCAD Sentaurus to investigate its electrical and thermal characteristics. The temperature and electric field-dependent electron mobility model is incorporated to predict I – V characteristics of the FET, which are in good agreement with the measured I – V characteristics. We investigated the effect of bias voltages on an electric field, a cur...
Measurement results of the terminal capacitances of a high-voltage power GaN high-electron-mobility transistor on a conductive-Si substrate are presented. These results show significant dependence of these capacitances on the substrate (or bulk/backside) voltage. In this article, we enhance the ASM-GaN compact model, which is a recently selected industry standard model for GaN devices, to account for this dependence. A detailed description of the modeling procedure is presented. Simulation resul...
We analyze the switching and retention properties of 65-nm integrated Cu(-Ge-Te)/(Ta)/GeSe conductive bridge random access memory devices operated at 50~\mu \text{A}. We evidence the crucial role played by a Ta buffer layer inserted between the Cu alloy and GeSe layers in decreasing the preforming current and in significantly improving the low-resistance state retention. Cu alloys of different compositions are tested to reveal lower device variability and longer retention with Cu2GeTe3 active...
The state-of-the-art superjunction (SJ) MOSFETs are based on the p-n pillar structures, arranged in a 2-D stripe geometry. This arrangement uses the superposition of the electric field components at the p-n junctions to create an enhanced depletion volume for higher breakdown capability. In this article, we will discuss structures, which additionally use the component of the electric field in the third dimension, to further enhance the depletion space. This allows higher doping concentrations in...
#1Kejun XiaH-Index: 2
#2Colin C. McAndrewH-Index: 16
Last.A.J. ScholtenH-Index: 17
view all 5 authors...
This article presents PSPHV, a surface-potential-based compact model for laterally diffused MOS (LDMOS) transistors. PSPHV includes a new drain voltage scaling technique that enables accurate modeling of saturation in transistors with nonuniform lateral doping; gate bias-dependent interface charge, which models the gradual channel turn- ON seen in devices with halo doping; internal drain bias clamping, which eliminates the capacitance spikes seen in most existing LDMOS models; and a new avalanch...
Josephson junction FETs (JJ-FETs) share design similarities with MOSFETs, except for the source/drain contacts being replaced by superconductors. Similarly, the super current due to proximity effect is tunable by the gate voltage. In light of recent advances in novel materials and fabrication techniques, we examine here the feasibility of JJ-FET-based Boolean logic and memory elements for cryogenic computing. Using a 2-D ballistic transport JJ-FET model, we implement circuit-level simulations fo...
This article deals with the monolithic integration in silicon of a multiphase static power converter (dc/ac or ac/dc) for medium power applications, from few kilowatts to few tens of kilowatts with power devices’ blocking capability in the range of 600–1200 V. This article presents an original three-chip integration approach that combines both monolithic integration in silicon and printed circuit board (PCB) packaging process and takes advantage of both silicon-level technology and PCB-level tec...
Multistage depressed collectors (MDCs) of traveling-wave tubes (TWTs) are used to collect kinetic power of a spent electron beam, recover part of this power to a useful electric power, and, by such a way, enhance the overall efficiency of TWTs. The heat-dissipation performance of MDCs is crucial. This brief presents a method for measuring the heat-dissipation characteristics of an MDC using an external heat source and a heat monitor. This method uses thermal transient testing techniques to measu...
We report the enhancement of carbon nanotube (CNT) field emitters by growing them directly on stripe-patterned alloy substrates. For a gate voltage of 1300 V, CNT field emitters grown on full and stripe-patterned alloy substrates achieved respective emission currents of 0.22 and 2.32 mA, corresponding to tenfold performance enhancement. Performance enhancement is attributed to the reduced screening effect (as a result of the spacing between strips) during field emission and a damage-free pattern...
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