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Soontae Kim
KAIST
85Publications
16H-index
819Citations
Publications 85
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In embedded systems such as automotive systems, multi-core processors are expected to improve performance and reduce manufacturing cost by integrating multiple functions on a single chip. However, inter-core interference in shared last-level cache (LLC) results in increased and unpredictable execution times for time-sensitive tasks (TSTs), which have (soft) timing constraints, thereby increasing the deadline miss rates of such systems. In this paper, we propose a time-sensitivity-aware dead bloc...
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#1Won-Young Lee (KAIST)H-Index: 5
#2Mincheol Kang (KAIST)H-Index: 2
Last.Soontae Kim (KAIST)H-Index: 16
view all 4 authors...
During the past decade, the endurance of NAND flash memory has severely deteriorated. The maximum number of program and erase cycles has fallen significantly with emerging of multilevel cell (MLC) and triple-level cell (TLC) technology, and scaling down of the cell size. Wear leveling is a general solution used to alleviate this issue; it enables cells to wear down evenly but it cannot actually mitigate the wearing of the cells. Accordingly, techniques are required to minimize the actual cell de...
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#1Jungwoo Park (KAIST)H-Index: 1
#2Myoungjun Lee (KAIST)H-Index: 1
Last.Jeongkyu HongH-Index: 2
view all 5 authors...
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#1Muhammad Avais Qureshi (KAIST)H-Index: 1
#2Hyeonggyu Kim (KAIST)H-Index: 5
Last.Soontae Kim (KAIST)H-Index: 16
view all 3 authors...
Spin-transfer torque RAM (STT-RAM) caches are foreseen to replace traditional static RAM caches because of their nonvolatile nature and high density. Multilevel cell (MLC) STT-RAMs further enhance the storage density of single-level cell STT-RAMs. However, the two-step read/write process in MLC STT-RAMs adversely affects performance, energy consumption, and lifetime. Moreover, technology scaling makes the read operations disturb the stored data in MLC STT-RAMs, giving rise to an issue called rea...
2 CitationsSource
Nov 1, 2018 in PACT (International Conference on Parallel Architectures and Compilation Techniques)
#1Jeongkyu Hong (Yeungnam University)H-Index: 2
#2Hyeonggyu Kim (KAIST)H-Index: 5
Last.Soontae Kim (KAIST)H-Index: 16
view all 3 authors...
Continuous DRAM scaling and integration is making refresh operations not scalable because more rows have to be refreshed in the same refresh interval. Thus, refresh operations are expected to consume more power in future DRAMs. To alleviate this problem, we propose a compression-based refresh-reducing DRAM architecture. To exploit prevalent zero and small memory values, we devise a novel 2-D ZERO compression scheme to increase compression coverage significantly with simple hardware support. 2-D ...
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#1Mincheol Kang (KAIST)H-Index: 2
#2Won-Young Lee (KAIST)H-Index: 5
Last.Soontae Kim (KAIST)H-Index: 16
view all 3 authors...
The manufacturers of NAND flash-based solid-state drives (SSDs) are increasing capacity and throughput by enlarging their page size, which is the minimum I/O unit in the NAND flash chips. Because the host and NAND flash chips have different I/O granularity units, the number of subpage requests increases. However, these subpage requests, especially writes, can cause internal fragmentation and endurance problems. Furthermore, subpage write requests inevitably involve read-modify-write (RMW) operat...
2 CitationsSource
#1Hyeonggyu Kim (KAIST)H-Index: 5
#2Minho Ju (Samsung)H-Index: 2
Last.Soontae Kim (KAIST)H-Index: 16
view all 3 authors...
Network errors such as packet losses consume large amounts of energy. We analyzed the reason for this through measurements using the latest smartphones and full-system simulation. We found that on packet losses the smartphones maintain high frequencies for CPU without doing useful work. To address this problem, we propose a method for reducing the energy consumption by lowering the performance level by exploiting a dynamic voltage and frequency scaling mechanism when long network delays are expe...
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Numerous functionalities are provided by smartphones and prolonging their battery lifetime is an undeniably critical support issue. In this article, we propose a low-power scheme called unnecessary region freezing (URF) that achieves significant total power consumption reduction in smartphones by reducing unnecessary drawing computation that originates from a user’s uninteresting display region. Moreover, we devise a user interface that helps the user to use our scheme flexibly and easily. We im...
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#1Jesung Kim (KAIST)H-Index: 3
#2Jongmin Lee (KAIST)H-Index: 5
Last.Soontae Kim (KAIST)H-Index: 16
view all 3 authors...
Conventional cache tag matching identifies the requested data based on a memory address. However, this address-based tag matching is inefficient because it requires unnecessarily many tag bits. Previous studies show that translation look-aside buffer (TLB) index-based tagging (TLBIT) can be adopted in instruction caches because there are not many different tags at a given moment due to spatial locality, and those tags can be captured by TLBs. For the TLBIT scheme, extra TLB indices are added to ...
2 CitationsSource
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