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Avinash Karanth Kodi
Ohio University
110Publications
16H-index
817Citations
Publications 110
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Travis Boraten3
Estimated H-index: 3
(Ohio University),
Avinash Karanth Kodi16
Estimated H-index: 16
(Ohio University)
As aggressive scaling continues to push multiprocessor system-on-chips (MPSoCs) to new limits, complex hardware structures combined with stringent area and power constraints will continue to diminish reliability. Waning reliability in integrated circuits will increase the susceptibility of transient and permanent faults. There is an urgent demand for adaptive error correction coding (ECC) schemes in network-on-chips to provide fault tolerance and improve overall resiliency of MPSoC architectures...
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Travis Boraten3
Estimated H-index: 3
(Ohio University),
Avinash Karanth Kodi16
Estimated H-index: 16
(Ohio University)
Abstract As Multiprocessor System-on-Chips (MPSoCs) continue to scale, security for Network-on-Chips (NoCs) is a growing concern as rogue agents threaten to infringe on the hardware’s trust and maliciously implant Hardware Trojans (HTs) to undermine their reliability. The trustworthiness of MPSoCs will rely on our ability to detect Denial-of-Service (DoS) threats posed by the HTs and mitigate HTs in a compromised NoC to permit graceful network degradation. In this paper, we propose a new light-w...
Ref 23Cited 1
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Scott Van Winkle1
Estimated H-index: 1
(Ohio University),
Avinash Karanth Kodi16
Estimated H-index: 16
(Ohio University),
Razvan C. Bunescu18
Estimated H-index: 18
(Ohio University)
... more
As communication energy exceeds computation energy in future technologies, traditional on-chip electrical interconnects face fundamental challenges in the many-core era. Photonic interconnects have been proposed as a disruptive technology solution due to superior performance per Watt, distance independent energy consumption and CMOS compatibility for on-chip interconnects. Static power due to the laser being always switched on, varying link utilization due to spatial and temporal traffic fluctua...
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Mark Clark (Ohio University), Avinash Karanth Kodi16
Estimated H-index: 16
(Ohio University),
Razvan C. Bunescu18
Estimated H-index: 18
(Ohio University)
... more
Network on Chips (NoCs) are the interconnect fabric of choice for multicore processors due to their superiority over traditional buses and crossbars in terms of scalability. While NoC’s offer several advantages, they still suffer from high static and dynamic power consumption. Dynamic Voltage and Frequency Scaling (DVFS) is a popular technique that allows dynamic energy to be saved, but it can potentially lead to loss in throughput. In this paper, we propose LEAD - Learning-enabled Energy-Aware ...
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Scott Vanwinkle (Ohio University), Avinash Karanth Kodi16
Estimated H-index: 16
(Ohio University)
As the relentless quest for higher throughput and lower energy cost continues in heterogenous multicores, there is a strong demand for energy-efficient and high-performance Network-on-Chip (NoC) architectures. Heterogeneous architectures that can simultaneously utilize both the serialized nature of the CPU as well as the thread level parallelism of the GPU are gaining traction in the industry. A critical issue with heterogeneous architectures is finding an optimal way to utilize the shared resou...
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Avinash Karanth Kodi16
Estimated H-index: 16
(Ohio University),
Kyle Shifflet (Ohio University), Savas Kaya16
Estimated H-index: 16
(Ohio University)
... more
As technology scales, hundreds and thousands of cores are being integrated on a single-chip. Since metallic interconnects may not scale effectively to support thousands of cores, architects have proposed emerging technologies such as photonics and wireless for intra-chip communication. While photonics technology is limited by the complexity and thermal effects, wireless technology for on-chip communication is limited by the available bandwidth. In this paper, we combine the benefits of both tech...
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Seaghan Sefton (Ohio University), Taiman Siddiqui (Ohio University), Nathaniel St. Amour (Ohio University)... more
Runtime monitors detect vulnerabilities in embedded systems by running alongside untrusted software in order to detect violations of security policies as they occur, ideally with minimal overhead. Prior work has demonstrated language support for largely static security policies implemented using lattices and tag-based monitors. However, compiling high-level policies to modular hardware monitors that can implement a wide variety of security policies with minimal power has not been previously prop...
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Travis Boraten3
Estimated H-index: 3
(Ohio University),
Avinash Karanth Kodi16
Estimated H-index: 16
(Ohio University)
Timing channel attacks use interference from contending application flows to cause information leakage, and thereby either covertly transmit secrets, or create Denial-of-Service (DoS) attacks to undermine the on-chip hardware security. Protecting against timing channel attacks is very challenging since unseen vulnerabilities emerge in newer technology that can be cleverly exploited by malicious applications by intentionally gaming resources to artificially induce interference. In this paper, we ...
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Talha Furkan Canan (Ohio University), Savas Kaya16
Estimated H-index: 16
(Ohio University),
Avinash Karanth Kodi16
Estimated H-index: 16
(Ohio University)
... more
Novel ultra-compact sub-10nm XOR, NOR and NAND CMOS logic circuits based on ambipolar characteristics of Schottky-Barrier (SB) FinFET devices and gate metal workfunction engineering are introduced. Use of SB source and drain contacts, high-k gate dielectrics and ultra-thin body bestows extreme short-channel immunity to the proposed FinFETs with ambipolar current-voltage characteristics. Thus, the main physical parameter left for practical device design and threshold control is the gate workfunct...
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Junqiang Wu1
Estimated H-index: 1
(University of Arizona),
Avinash Karanth Kodi16
Estimated H-index: 16
(Ohio University),
Savas Kaya16
Estimated H-index: 16
(Ohio University)
... more
We propose a novel antenna design enabled by 3-D printing technology for future wireless intrachip interconnects aiming at applications of multicore architectures and system-on-chips. In our proposed design we use vertical quarter-wavelength monopoles at 160 GHz on a ground plane to avoid low antenna radiation efficiency caused by the silicon substrate. The monopoles are surrounded by a specially designed dielectric property distribution. This additional degree of freedom in design enabled by 3-...
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