Avinash Karanth Kodi
Ohio University
112Publications
16H-index
845Citations
Publications 112
Newest
Published on Dec 1, 2018
Talha Furkan Canan (Ohio University), Savas Kaya16
Estimated H-index: 16
(Ohio University)
+ 2 AuthorsAhmed Louri19
Estimated H-index: 19
(George Washington University)
We introduce novel ten (10T) and eight (8T) transistor full-adder logic gates based on recently proposed gate workfunction engineering (WFE) approach. When applied to sub-10 nm Schottky-barrier (SB) independent-gate FinFETs, WFE leads to hitherto unexplored 4T and 3T XOR implementations that operate with either only one or no inverted input, respectively. The novel 4T and 3T XOR gates eliminate the need for inverted inputs provided that ambipolar I-V characteristics is shifted by the associated ...
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Published on Aug 1, 2018
Yunus Kelestemur (Ohio University), Soumyasanta Laha5
Estimated H-index: 5
(Ohio University)
+ 3 AuthorsAhmed Louri19
Estimated H-index: 19
(George Washington University)
This paper investigates the properties of sub-THz compact tunable push-push oscillator in 45 nm FinFET technology. The push-push oscillator is designed to operate at 250 GHz in a modified cross-coupled LC topology. Commanding the FinFET gates separately in independent-mode bestows the push-push oscillator with a simple and efficient means for ~ 5 GHz tunable performance without external varactors. Moreover, due to the increased transconductance, the stability criteria of oscillation is much rela...
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Published on May 1, 2018
Avinash Karanth Kodi16
Estimated H-index: 16
(Ohio University),
Kyle Shifflet (Ohio University)+ 2 AuthorsAhmed Louri19
Estimated H-index: 19
(George Washington University)
As technology scales, hundreds and thousands of cores are being integrated on a single-chip. Since metallic interconnects may not scale effectively to support thousands of cores, architects have proposed emerging technologies such as photonics and wireless for intra-chip communication. While photonics technology is limited by the complexity and thermal effects, wireless technology for on-chip communication is limited by the available bandwidth. In this paper, we combine the benefits of both tech...
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Seaghan Sefton (Ohio University), Taiman Siddiqui (Ohio University)+ 2 AuthorsAvinash Karanth Kodi16
Estimated H-index: 16
(Ohio University)
Runtime monitors detect vulnerabilities in embedded systems by running alongside untrusted software in order to detect violations of security policies as they occur, ideally with minimal overhead. Prior work has demonstrated language support for largely static security policies implemented using lattices and tag-based monitors. However, compiling high-level policies to modular hardware monitors that can implement a wide variety of security policies with minimal power has not been previously prop...
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Published on Jan 1, 2018in Journal of Parallel and Distributed Computing 1.81
Travis Boraten3
Estimated H-index: 3
(Ohio University),
Avinash Karanth Kodi16
Estimated H-index: 16
(Ohio University)
Abstract As Multiprocessor System-on-Chips (MPSoCs) continue to scale, security for Network-on-Chips (NoCs) is a growing concern as rogue agents threaten to infringe on the hardware’s trust and maliciously implant Hardware Trojans (HTs) to undermine their reliability. The trustworthiness of MPSoCs will rely on our ability to detect Denial-of-Service (DoS) threats posed by the HTs and mitigate HTs in a compromised NoC to permit graceful network degradation. In this paper, we propose a new light-w...
1 Citations Source Cite
Published on Feb 1, 2018 in High-Performance Computer Architecture
Scott Van Winkle1
Estimated H-index: 1
(Ohio University),
Avinash Karanth Kodi16
Estimated H-index: 16
(Ohio University)
+ 1 AuthorsAhmed Louri19
Estimated H-index: 19
(George Washington University)
As communication energy exceeds computation energy in future technologies, traditional on-chip electrical interconnects face fundamental challenges in the many-core era. Photonic interconnects have been proposed as a disruptive technology solution due to superior performance per Watt, distance independent energy consumption and CMOS compatibility for on-chip interconnects. Static power due to the laser being always switched on, varying link utilization due to spatial and temporal traffic fluctua...
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Published on Jun 24, 2018 in Design Automation Conference
Mark Clark (Ohio University), Avinash Karanth Kodi16
Estimated H-index: 16
(Ohio University)
+ 1 AuthorsAhmed Louri19
Estimated H-index: 19
(George Washington University)
Network on Chips (NoCs) are the interconnect fabric of choice for multicore processors due to their superiority over traditional buses and crossbars in terms of scalability. While NoC’s offer several advantages, they still suffer from high static and dynamic power consumption. Dynamic Voltage and Frequency Scaling (DVFS) is a popular technique that allows dynamic energy to be saved, but it can potentially lead to loss in throughput. In this paper, we propose LEAD - Learning-enabled Energy-Aware ...
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Scott Vanwinkle (Ohio University), Avinash Karanth Kodi16
Estimated H-index: 16
(Ohio University)
As the relentless quest for higher throughput and lower energy cost continues in heterogenous multicores, there is a strong demand for energy-efficient and high-performance Network-on-Chip (NoC) architectures. Heterogeneous architectures that can simultaneously utilize both the serialized nature of the CPU as well as the thread level parallelism of the GPU are gaining traction in the industry. A critical issue with heterogeneous architectures is finding an optimal way to utilize the shared resou...
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Published on Oct 4, 2018
Travis Boraten3
Estimated H-index: 3
(Ohio University),
Avinash Karanth Kodi16
Estimated H-index: 16
(Ohio University)
Timing channel attacks use interference from contending application flows to cause information leakage, and thereby either covertly transmit secrets, or create Denial-of-Service (DoS) attacks to undermine the on-chip hardware security. Protecting against timing channel attacks is very challenging since unseen vulnerabilities emerge in newer technology that can be cleverly exploited by malicious applications by intentionally gaming resources to artificially induce interference. In this paper, we ...
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Travis Boraten3
Estimated H-index: 3
(Ohio University),
Avinash Karanth Kodi16
Estimated H-index: 16
(Ohio University)
As aggressive scaling continues to push multiprocessor system-on-chips (MPSoCs) to new limits, complex hardware structures combined with stringent area and power constraints will continue to diminish reliability. Waning reliability in integrated circuits will increase the susceptibility of transient and permanent faults. There is an urgent demand for adaptive error correction coding (ECC) schemes in network-on-chips to provide fault tolerance and improve overall resiliency of MPSoC architectures...
3 Citations Source Cite
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